This invention relates to an integrating type digital-analog (D-A)/analog-digital (A-D) converter, and more particularly to an integrating type D-A/A-D converter adapted for controlling an integral time in accordance with a plurality of reference clocks having periods which are different from each other and are such that the time length relationship therebetween is indicated by an arbitrary integer ratio, thereby permitting the conversion processing time to be reduced.
The integrating type D-A/A-D converter is one of high accuracy and effective D-A/A-D converting means in the technical field where the D-A or A-D conversion speed is relatively low.
Initially, explanation will be given with respect to the conventional D-A converter by using FIGS. 1-3. FIG. 1 shows the outline the configuration of a conventional D-A converter of the single slope type. In the figure, the D-A converter comprises a control circuit 1 adapted to receive a plurality of digital input signals to control its integral time, a reference voltage generation circuit 8 for delivering an analog reference voltage V.sub.ref synchronous with the digital input by the control circuit 1, an integration circuit 10 for integrating the reference voltage V.sub.ref delivered by a predetermined timing, and a reset circuit 15 for clearing an output of the integration circuit 10. The control circuit 1 comprises a timing controller 2, a clock circuit 3 adapted to generate a single clock having a single period to deliver it to the timing controller 2, and a connection circuit 4 comprised of a switch SW.sub.1 provided between the reference voltage generation circuit 8 and the integration circuit 10 and adapted for opening and closing the circuit so as to deliver the reference voltage V.sub.ref to the integration circuit 10 in accordance with a timing set by the timing controller 2.
The integration circuit 10 comprises an operational amplifier 11 adapted to input an analog reference voltage delivered only for a time period proportional to a digital input 6 to carry out integrating operation (calculation) to output an arbitrary function as an analog output 16, a capacitor 12 connected in parallel with the operational amplifier 11, and a resistor 13 provided between the connection circuit 4 and the operational amplifier 11. The reset circuit 15 is comprised of a reset switch SW.sub.R for short-circuiting the both ends of the capacitor 12 of the integration circuit 10 to thereby clear an output of the operational amplifier 11.
The operation based on the above-described configuration will now be described. Initially, prior to inputting a digital value 6, an output of the operational amplifier 11 of the integration circuit 10 is in advance cleared by allowing the reset switch SW.sub.R of the reset circuit 15 to be turned ON. Then, the reset switch SW.sub.R is caused to be turned OFF to allow the switch SW.sub.1 of the connection circuit 4 to be turned ON only for a time period proportional to the digital value 6 to be converted to thereby deliver the reference voltage V.sub.ref to the operational amplifier 11 to perform an integrating operation, thus making it possible to obtain an analog output 16 proportional to the digital input value 6. To realize this, the timing controller 2 receives the digital input 6 and also receives a clock signal generated by the clock circuit 3 thus to control an ON/OFF time of the switch SW.sub.1 of the connection circuit 4.
The integrating type D-A converter constructed and operated as above is based on the principle to convert the conversion resolution from a digital value to an analog value in correspondence with the integral time. The time required for integrating a digital value per unit is a period of a reference clock, and an integrated value integrated by the period of the reference clock is a unit analog value. Since the period of the reference clock and the unit analog value determine accuracy of the D-A conversion, it is impossible in principle to output an analog value smaller than an integral value integrated by the period of the reference clock.
Moreover, since the integrating type D-A converter allows an integral value obtained by carrying out integration only for a time proportional to a digital input value to be an analog output, it is necessary for carrying out D-A conversion processing at a high speed to shorten (reduce) the period of the reference clock so as to shorten the conversion time.
For example, in D-A converters used in the audio field, there are some D-A converters operative at a sampling frequency of 48 kHz. In the case of applying D-A conversion to a digital input with the accuracy of 16 bits, a reference clock having a frequency of 3.15 GHz is required. However, since it is difficult in practice to generate such a high speed reference clock, it was unable to operate the integrating type D-A converter of this system at a sampling frequency of 48 kHz and with the accuracy of 16 bits of a digital input.
To improve the above-mentioned drawback, a D-A converter of the dual slope type as shown in FIG. 2 has been proposed. In this D-A converter, the reference voltage generation circuit 8 is composed of first and second voltage sources 8a and 8b adapted for outputting first and second reference voltages V.sub.ref1 and V.sub.ref2 having different two values, respectively. Further, switch SW.sub.1 constituting the connection circuit 4 of the control circuit 1 includes terminals 4a and 4b for switching between voltage sources 8a and 8b. Other components are similar to those of the D-A converter of the single slope type of FIG. 1.
The dual slope type D-A converter thus constructed operates, in a manner similar to that of the single slope type D-A converter shown in FIG. 1, to first close the reset switch SW.sub.R of the reset circuit 15 to short-circuit the both ends of capacitor 12 to thereby clear an output of the operational amplifier 11. Then, the movable contact of the changeover switch SW.sub.1 of the connection circuit 4 is caused to be operative to close the contact 4a on the first reference voltage source 8a side. Thus, the first reference voltage V.sub.ref1 is used to carry out a first integration. Then, the movable contact of the changeover switch SW.sub.1 is switched to the contact 4b side on the second reference voltage source 8b side to deliver the second reference voltage V.sub.ref2 to integration circuit 10. Thus, a second integration is carried out. The relationship between an output voltage V.sub.0 of the analog output 16 integrated by the integration circuit 10 and the integration time periods t.sub.1 and t.sub.2 is shown in FIG. 3. Since gradients for the integration time periods t.sub.1 and t.sub.2 are different from each other, a D-A converter having two kinds of reference voltages V.sub.ref1 and V.sub.ref2 is called a dual slope type D-A converter.
Assuming now that the period of a single reference clock outputted from the clock circuit 3 is .DELTA.t, the time period during which integration is carried out by the first reference voltage V.sub.ref1 is t.sub.1, and the time period during which integration is carried out by the second reference voltage V.sub.ref2 is t.sub.2, the relationship expressed as "t.sub.1 =n.times..DELTA.t" and "t.sub.2 =m.times..DELTA.t" holds. n and m are constants different from each other. Accordingly, when it is assumed that the capacity of the capacitor 12 is C, and the resistance of a resistor 13 is R, an output voltage V.sub.0 is calculated by the following formula: ##EQU1##
In the above formula (1), if "V.sub.ref1 &gt;V.sub.ref2 " holds, an approach is employed to roughly carry out integration by the reference voltage V.sub.ref1 up to a value close to the target output voltage V.sub.0 thereafter to carry out integration by the reference voltage V.sub.ref2, thereby making it possible to carry out D-A conversion with the integral time being caused to be shorter than that of the single slope type D-A converter.
However, since relative accuracy between different reference voltages V.sub.ref1 and V.sub.ref2 is rigorously required for the above-mentioned dual slope type D-A converter, if a relative output voltage between reference voltages is different from a set value, any error would take place between an integral value output voltage V.sub.0 calculated by the formula (1) and a target output voltage. Namely, there was the drawback that if the relative accuracy between two reference voltages V.sub.ref1 and V.sub.ref2 deteriorated, any error, etc. relating to the differential linearlity of an integral output takes places, thus causing the D-A conversion accuracy to be lowered.
A conventional integrating type A-D converter will now be described.
FIG. 4 shows the outline of the configuration of a dual ramp type A-D converter which is of the conventional typical type. In FIG. 4, the A-D converter includes, similarly to the D-A converter, control circuit 1, reference voltage generation circuit 8, integration circuit 10, and reset circuit 15. Since the A-D converter includes many components common to those of the D-A converter as the fundamental configuration, explanation will be given with different reference numerals being attached only to different components. Connection circuit 4 of the control circuit 1 comprises a switch 14 for carrying out ON/OFF control of supply to the integration circuit 10 of an analog input 7, and a switch 4a for carrying out ON/OFF control of supply to the integration circuit 10 of the reference voltage V.sub.ref. The control circuit 1 includes clock circuit 3 for delivering a clock having a single period to the timing controller 2, and the clock of this clock circuit 3 is delivered also to a counter 5. An integral output of the integration circuit 10 is delivered to a comparator 18, at which it is compared with a reference potential. Its output is delivered to the counter 5. This counter 5 converts an inputted potential to digital values 17 on the basis of the clock to output it.
The operation of the A-D converter thus constructed will now be described. Similarly to the D-A converter, reset switch SW.sub.R of the reset circuit 15 is closed to short-circuit the both ends of the capacitor 12 to clear an integrated output of the operational amplifier 11. Then, the reset switch SW.sub.R is caused to be turned OFF to allow the switch 14 of the connection circuit 4 to be turned ON on the basis of a signal from the timing controller 2, whereby an input voltage V.sub.i of the analog input 7 is delivered to the integration circuit 10. Thus, the integration circuit 10 starts integration of an input voltage to carry out integration only for a time period set in advance, thereby making it possible to provide a voltage proportional to the input voltage V.sub.i as an output of the integration circuit 10. When the switch 14 of the connection circuit 4 is caused to be turned OFF and the switch 4a is caused to be turned ON, reference voltage V.sub.ref delivered from the reference voltage generation circuit 8 is delivered to the integration circuit 10. Thus, the integration circuit 10 integrates the reference voltage V.sub.ref in a direction opposite to that of the input voltage V.sub.i. At this time, since the reference voltage V.sub.ref is fixed, the integration circuit 10 carries out a fixed integrating operation. Its integrated output is indicated by a fixed gradient at all times. Accordingly, a time required until the integrated output of the integration circuit 10 becomes equal to "0" for a second time is measured, thereby making it possible to convert an inputted potential to a digital value. The integrating type A-D converter of this system is the most fundamental, and is called an A-D converter of the dual ramp type because the integrating direction of the input voltage and that of the reference voltage are opposite to each other and combination of two gradients of integrated outputs indicates mountain shape.
Because the dual ramp type A-D converter converts the conversion resolution to time similarly to the single slope type D-A converter, it is necessary to shorten the reference clock period in order to permit high speed A-D conversion to shorten the conversion time. This restricted realization of high speed operation. To solve this, also in the A-D converter, there has been proposed a triple ramp type A-D converter constructed to deliver a plurality of different reference voltages so that an integrated output has three gradients.
The outline of the configuration of the triple ramp type A-D converter is shown in FIG. 5. In FIG. 5, since the configurations of the integration circuit 10, the reset circuit 15 and the comparator 18 are the same as those of respective components in FIG. 4, their explanation will be omitted. The A-D converter of FIG. 5 includes first and second reference voltage sources 8a and 8b for respectively outputting first and second reference voltages V.sub.ref1 and V.sub.ref2 similarly to the reference voltage generation circuit 8 of The D-A converter of FIG. 2. The connection circuit 4 includes a switch 14 for delivering an analog input 7 to the integration circuit 10, and a switch SW.sub.1 having a movable contact 4A and two fixed contacts 4a and 4b for carrying out switching between first and second reference voltages V.sub.ref1 and V.sub.ref2 every predetermined time to deliver a switched voltage to the integration circuit.
The operation of the triple ramp type A-D converter thus constructed will now be described in accordance with FIGS. 5 and 6. Initially, when the switch SW.sub.R of the reset circuit 15 is closed, the both ends of the capacitor 12 are short-circuited, whereby an integrated output of the operational amplifier 11 is cleared. When the switch SW.sub.R is opened and the switch 14 of an analog input is closed with the movable contact 4A of the switch SW.sub.1 of the connection circuit 4 being also in an open state, the analog input 7 is delivered to the integration circuit 10, so integration of the analog input voltage is carried out only for an integral time period t.sub.0 of FIG. 6. Further, when the switch 14 is opened and the movable contact 4A of the switch SW.sub.1 is connected to the fixed contact 4a on the first reference voltage source 8a side, first reference voltage V.sub.ref1 having a direction opposite to that of the analog input voltage is delivered to the integration circuit 10, so integration is carried out only for a time period indicated by the integration time period t.sub.1 in FIG. 6. Then, the movable contact 4A of the switch SW.sub.1 is switched to the fixed contact 4b side on the second reference voltage source 8b side, so the second reference voltage V.sub.ref2 is delivered to the integration circuit 10. Thus, only for the integration time period t.sub.2 of FIG. 6, an integrated output having a direction opposite to that of the analog input voltage and a gradient different from that of the first reference voltage is provided by calculation (operation) until it becomes equal to "0". At this time, when it is assumed that "V.sub.ref1 &gt;V.sub.ref2 " holds, the higher order bits are determined by a time obtained by integrating the first reference voltage V.sub.ref1, and the lower order bits are determined by a time obtained by integrating the second reference voltage V.sub.ref2. Accordingly, it is possible to increase the resolution of the integration circuit 10 without increasing the clock frequency.
When it is now assumed as shown in FIG. 6 that the time during which integration of an analog input voltage is carried out is t.sub.0, the time during which integration of the first reference voltage V.sub.ref1 is carried out is t.sub.1, the time during which integration of the second reference voltage V.sub.ref2 is carried out is t.sub.2, and the clock period is .DELTA.t, the relationship expressed as "t.sub.O =P.times..DELTA.t", "t.sub.1 =n.times..DELTA.t", and "t.sub.2 =m.times..DELTA.t" (P, n, m are constants) holds. From this relationship, the input voltage V.sub.i is calculated by the following formula (2): ##EQU2## Accordingly, also in the A-D converter similarly to the D-A converter, even if a low clock frequency is used, it is possible to obtain a resolution of high accuracy, and to carry out A-D conversion at a high speed.
However, also in the conventional triple ramp type A-D converter constructed and operated as above, there is the problem that when the relative accuracy between first and second reference voltages V.sub.ref1 and V.sub.ref2 is deteriorated, the conversion accuracy of the differential linearlity, etc. is lowered.
As stated above, in the conventional D-A/A-D converters, even if a D-A/A-D converter of any type is employed, the D-A/A-D conversion accuracy is restricted by the period of the reference clock. As a result, it was impossible to obtain an analog value smaller than an integral value corresponding to the period of the reference clock as an output of the integration circuit.
Further, in order to cause the D-A/A-D converter to be operative at a high speed, it is necessary to allow the clock frequency to be high. However, because it is impossible to allow the clock frequency to be high without any restriction in practice, there is limitation in reducing the conversion processing time of the converter.
In addition, in the case where the dual slope type D-A converter or the triple ramp type A-D converter is used in order to practically shorten the conversion processing time of the converter, the relative accuracy between plural reference voltages may be deteriorated. As a result, there was also the problem that, e.g., the differential linearlity, etc. may be deteriorated, thus causing the conversion accuracy to be lowered.